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Handle RISC-V CPU Manufacturer and Brand using uarch in /proc/cpuinfo

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In the RISC-V world, CPUs are often designed by companies like SiFive, T-Head and Andes.
Use the /proc/cpuinfo 'uarch' values to get the CPU designer and CPU model.

These designs are then licensed to SoC manufacturers who add I/O and GPU features.
For example Allwinner (D1) and StarFive (JH7110), and Sophgo (SG2000)
This commit is contained in:
Roger Hardiman 2024-04-16 12:09:46 +00:00
parent b4bc62bef9
commit 62e07052bd
1 changed files with 14 additions and 0 deletions
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14
lib/cpu.js
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@ -605,6 +605,9 @@ function cpuManufacturer(str) {
if (str.indexOf('Xen') >= 0) { result = 'Xen Hypervisor'; }
if (str.indexOf('tcg') >= 0) { result = 'QEMU'; }
if (str.indexOf('apple') >= 0) { result = 'Apple'; }
if (str.indexOf('sifive') >= 0) { result = 'SiFive'; }
if (str.indexOf('thead') >= 0) { result = 'T-Head'; }
if (str.indexOf('andestech') >= 0) { result = 'Andes Technology'; }
return result;
}
@ -788,6 +791,17 @@ function getCpu() {
}
}
// Test RISC-V
if (util.getValue(lines, 'architecture') === 'riscv64') {
const linesRiscV = fs.readFileSync('/proc/cpuinfo').toString().split('\n');
const uarch = util.getValue(linesRiscV, 'uarch') || '';
if (uarch.indexOf(',') > -1) {
const split = uarch.split(',');
result.manufacturer = cpuManufacturer(split[0]);
result.brand = split[1];
}
}
// socket type
let lines2 = [];
exec('export LC_ALL=C; dmidecode –t 4 2>/dev/null | grep "Upgrade: Socket"; unset LC_ALL', function (error2, stdout2) {